STAR 50 Surges 3.18%—Record Daily Gain as Semiconductor Sector Enters Earnings Validation Phase

STAR 50 Index Surges Over 3% in a Single Day: A Landmark Signal That China’s Semiconductor Self-Reliance Has Entered Its “Earnings Realization Phase”

On May 20, the SSE STAR 50 Index surged 3.18%—its largest single-day gain on record. SMIC’s A-share stock skyrocketed 12.37%, while Cambricon, VeriSilicon, Toppan Photomasks, and Advanced Micro-Fabrication Equipment (AMEC) all hit their daily trading limits. The entire chip industry chain exhibited a rare “full-chain resonance”: design, fabrication, equipment, materials, packaging & testing, and EDA tools all rallied simultaneously. This rally is markedly distinct from prior theme-driven speculation: capital is shifting from policy expectations to tangible order fulfillment—and from conceptual narratives to financial statement validation. Underpinning this shift is a pivotal inflection point: China’s semiconductor self-reliance strategy is accelerating from top-level design into the deep waters of industrialization—and serving as a bellwether for a systemic revaluation of the TMT sector.

Policy Front: A Closed Loop Is Emerging—from Macro Declarations to Micro-Level Implementation

The National Development and Reform Commission (NDRC)’s May 20 symposium with private enterprises sent a clear signal: technological self-reliance and industrial-chain autonomy are no longer abstract goals—they have been embedded directly into operational frameworks aimed at “curbing ‘cutthroat’ domestic competition” and “expanding profitable investment.” NDRC Director Zheng Zhajie specifically invited Zhipu AI—a leading Chinese AI firm—to the meeting, underscoring the elevated policy priority of AI compute infrastructure, i.e., advanced-process chips. Notably, the symposium did not dwell on generalities; instead, it focused squarely on “how macro policies translate into concrete outcomes at the micro level.” This means specific implementation details—including subsidy disbursement schedules, green-channel procurement for domestic equipment, and timelines for domestic technology verification and market access—are now central metrics for evaluating policy effectiveness.

Meanwhile, the U.S.–China trade talks’ stated goal of “locking in results as soon as possible” objectively affords China’s semiconductor industry a precious window of opportunity. While the U.S. continues pressuring China on mature nodes, enforcement of export controls on equipment for 28nm and above has shown signs of de facto easing. According to insiders at a leading domestic foundry, the pass rate for domestic lithography and etching tools undergoing verification on mature-node production lines rose 40% in Q1 2024 versus 2023—and some tools have already entered pilot-volume production. Policy benefits are now flowing from “paper” to “production line”—a fundamental watershed distinguishing this rally from those seen in 2019 or 2022.

Capacity Expansion: AI Compute Demand Drives Dual-Track Growth in Advanced Packaging and Mature Nodes

Soaring global AI server shipments are reshaping the semiconductor manufacturing landscape. Counterpoint Research reports that global AI server shipments surged 126% year-on-year in Q1 2024—with Chinese vendors accounting for 38% of total volume. This surge directly fuels demand across two critical domains:

• Chiplet-based advanced packaging, essential for HBM memory stacking and GPU interconnects; and
• 28nm/40nm mature-node processes, used for AI server power management ICs, network PHY chips, and FPGA co-processors.

SMIC’s 12% single-day jump reflects dual market confirmation: successful yield ramp-up of its “N+2” process (functionally equivalent to TSMC’s 7nm), and the accelerated commissioning of its new Shenzhen 28nm fab (originally slated for Q1 2025, now expected in Q3 2024).

More critically, capacity expansion is dramatically improving visibility into upstream orders. For instance:

• NAURA’s new orders in Q1 2024 included 30% from advanced packaging equipment (e.g., TSV etch, RDL copper plating);
• Siltronic China (Shanghai Silicon Industry Corp.) reduced its large-diameter silicon wafer customer qualification cycle from 18 months to just 9 months;
• Anji Technology’s CMP slurries achieved a 35% localization rate in the memory chip segment—up 12 percentage points from end-2023.

Orders are no longer vague “three-year-out” projections—they are trackable quarterly delivery schedules.

Localization Rates: Equipment, Materials, and EDA Are Undergoing a Qualitative Leap—from “Zero to One” to “One to Ten”

Localization rates across key segments are now exhibiting differentiated inflection points:

• Equipment: Domestic etchers, cleaners, and thermal processing tools exceed 30% localization—but lithography and thin-film deposition remain below 10%. Yet Shanghai Micro Electronics’ 28nm lithography tool has entered verification at SMIC’s production line; if reliability testing clears in Q3, it will decisively break the “bottleneck” narrative.
• Materials: Localization rates for large-diameter silicon wafers, sputtering targets, and photoresist ancillary materials stand at 25%, 45%, and 18%, respectively. Notably, Ningbo Jiangfeng Electronics’ sputtering targets have entered TSMC’s supply chain—signaling formal entry of Chinese materials into global mainstream certification systems.
• EDA: Empyrean’s analog design tools cover 92% of the 28nm node—but full digital design flows still rely heavily on Synopsys. A cautionary note: In May, the U.S. Department of Commerce added AI-driven EDA tools to its export control list—an action ironically accelerating domestic M&A. Following its acquisition of Boda Micro, Primarius’ device modeling platform now supports FinFET processes below 5nm.

IDM-mode firms—including Silan Microelectronics and China Resources Microelectronics—are benefiting from vertical integration (“design–fabrication–packaging & testing”) to achieve profitability first in high-barrier niches like automotive MCUs and power semiconductors. Silan’s automotive-grade chip revenue surged 217% YoY in Q1 2024—evidence that localization has extended beyond consumer electronics into demanding industrial applications.

Valuation Reconfiguration: The TMT Sector Must Bid Farewell to “Price-to-Dream” and Embrace the New Paradigm of “Price-to-Sales + Order Backlog Multiple”

The STAR 50’s current rally reflects a fundamental recalibration of valuation anchors for China’s TMT sector. For the past decade, semiconductor firms were typically valued on Price-to-Sales (P/S) multiples—yet often lacked robust order visibility. Today, investors increasingly demand an “Order Backlog Multiple” (Backlog-to-Market-Cap Ratio)—the ratio of total undelivered orders to current market capitalization. Take AMEC: its Q1 2024 order backlog stood at ¥8.2 billion, yielding a backlog multiple of 0.9—well above the industry average of 0.4. This capacity-grounded valuation method forces analysts to conduct on-site factory visits and scrutinize foundry equipment scheduling—not merely parse financial statement language.

More profoundly, once the semiconductor sector completes its three-stage transition—from policy-driven → order-driven → profit-driven—its valuation center of gravity will converge toward industrial manufacturing benchmarks. Using TSMC’s current P/E of 22x as reference, if SMIC achieves the consensus analyst forecast of 45% net profit growth in 2024, its fair P/E range should rise to 18–22x. This would fundamentally redefine the A-share TMT sector’s longstanding “high-volatility, low-profitability” label—and provide a more solid hardware pricing foundation for downstream AI and cloud computing applications.

Conclusion: Rally Sustainability Hinges on the Steepness of the “Localization Rate Curve”

The STAR 50’s 3% single-day surge is not the start of a celebration—it marks the beginning of a stress test. Whether this rally endures hinges less on “the number of policy documents issued” and more on three granular, observable metrics:

• The installation share of domestic equipment in newly built fabs;
• The number of wafer fabs successfully qualifying domestic materials; and
• The actual usage rate of domestic EDA tools in tape-out projects.

When NAURA’s etching tools surpass 20 units installed at SMIC’s Beijing fab;
When Anji’s CMP slurries demonstrate a 0.3-percentage-point lower yield loss than international competitors at Yangtze Memory Technologies (YMTC);
When Empyrean’s EDA tools support chip tape-outs achieving >95% first-pass success rates—

only sustained improvement in such micro-level data can serve as the true bedrock for the index to ascend to a new plateau. China’s semiconductor self-reliance has finally arrived at a historic juncture: one where yield speaks, orders vote, and profits prove.